Approximate Accelera on for a Post Mul core Era

Approximate Accelera on for a Post Mul core Era Hadi Esmaeilzadeh Co-Chairs of the Supervisory Commi ee: Professor Doug Burger Microso Research Associate Professor Luis Ceze University of Washington Star ng in 2004, the microprocessor industry has shi ed to mul core scaling—increasing the number of cores per die each technology genera on—as its principal strategy for con nuing performance growth. This work first studies the interplay between the rise ofmul core processors and the rise ofmanaged languages— e.g. Java—in the past decade. Then, this disserta on looks into future, studies the trends in transistor scaling, and inves gates whether mul core scaling will sustain tradi onal performance improvements that have been the driving force for the en re compu ng industry over the past forty years. The results from our work challenges the conven onal wisdom that advocates mul core scaling is a viable path for exploi ng increased transistor counts and sustaining historical performance trends. As the number of cores increases, power constraints may prevent powering of all cores at their full speed, requiring a frac on of the cores to be powered off at all mes. According to our models, the frac on of these chips that is dark may be as much as 50% within three process genera ons. The low u lity of this dark silicon may prevent both scaling to higher core counts and ul mately the economic viability of con nued silicon scaling. Our study highlights that radical departures from conven onal approaches may be necessary to sustain the tradi onal rate of performance improvements in general-purpose compu ng. These techniques should provide significant performance and energy efficiency gains across a wide range of applica ons. This disserta on then proposes a new direc on for general-purpose compu ng that leverages approxima on to address the dark silicon challenge. While conven onal techniques—such as dynamic voltage and frequency scaling—trade performance for energy, general-purpose approximate compu ng trades error for both performance and energy gains. We propose variable-precision architectures, a framework from the ISA—Instruc on Set Architecture—to the transistorlevel implementa ons that allow conven onal von Neumann processors to trade accuracy for energy at the granularity of single instruc ons. Then, we propose an end-to-end solu on, from the programming model to the microarchitecture that leverages an approximate algorithmic transforma on to automa cally convert a hot code region from a von Neumannmodel to a neural model. This solu on and its associated algorithmic transforma on enables a new class of accelerators, called Neural Processing Units (NPUs) with implementa on poten al in both the digital and the analog domain. This work shows significant gains both in performance and energy when the abstrac on of full accuracy is relaxed in general-purpose compu ng. The results from this disserta on show that general-purpose approximate compu ng can be a path forward when the gains from conven onal approaches are diminishing.